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lt3579/lt3579-1 1 35791fa for more information www.linear.com/lt3579 typical application description 6a boost/inverting dc/dc converter with fault protection the lt ? 3579 is a pwm dc/dc converter with built-in fault protection features to aid in protecting against output shorts, input/output overvoltage, and overtemperature conditions. the part consists of a 42v master switch, and a 42v slave switch that can be tied together for a total current limit of 6a. the lt3579 is ideal for many local power supply designs. it can be easily conigured in boost, sepic, inverting, or flyback conigurations, and is capable of generating 12v at 1.7a, or C12v at 1.2a from a 5v input. in addition, the lt3579s slave switch allows the part to be conigured in high voltage, high power charge pump topologies that are very eficient and require fewer components than traditional circuits. the lt3579s switching frequency range can be set bet ween 200khz and 2.5mhz. the part may be clocked internally at a frequency set by the resistor from the rt pin to ground, or it may be synchronized to an external clock. a buffered version of the clock signal is driven out of the clkout pin, and may be used to synchronize other compatible switching regulator ics to the lt3579. the lt3579 also features innovative shdn pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. additional features such as frequency foldback and soft-start are integrated. the lt3579 is available in 20-lead tssop and 20-pin 4mm 5mm qfn packages. 1mhz, 5v to 12v boost converter with output short circuit protection features applications n 6a, 42v combined power switch n output short circuit protection n wide input range: 2.5v to 16v operating, 40v maximum transient n lt3579-1: dual-phase capable n master/slave (3.4a/2.6a) switch design n user conigurable undervoltage lockout n easily conigurable as a boost, sepic, inverting, or flyback converter n low v cesat switch: 250mv at 5.5a (typical) n can be synchronized to external clock n can synchronize other switching regulators n high gain shdn pin accepts slowly varying input signals n 20-lead tssop and 20-pin 4mm 5mm qfn packages n local power supply n vacuum fluorescent display (vfd) bias supplies n tft-lcd bias supplies n automotive engine control unit (ecu) power l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7579816. v in 5v 200k 100k 86.6k 22f 2.2h sw1 sw2 fb gate v c clkout v in v in rt sync gnd ss fault shdn 47pf temperature monitor lt3579 130k 2.2nf 10f v out 12v1.7a 6.3k 8k 0.1f 10f 35791 ta01 ef?ciency and power loss load current (a) 0 20 efficiency (%) power loss (w) 80 9070 60 50 40 30 100 0 2.4 2.82.0 1.6 1.2 0.8 0.4 3.2 0.25 1 1.25 1.5 1.75 2 0.5 35791 ta02 0.75 downloaded from: http:///
lt3579/lt3579-1 2 35791fa for more information www.linear.com/lt3579 pin configuration absolute maximum ratings v in voltage ................................................. C0.3v to 40v sw1/sw2 voltage ..................................... C0.4v to 42v r t voltage .................................................... C0.3v to 5v ss, fb voltage ......................................... C0.3v to 2.5v v c voltage ................................................... C0.3v to 2v shdn voltage ............................................ C0.3v to 40v sync voltage ............................................ C0.3v to 5.5v gate voltage ............................................. C0.3v to 80v (note 1) fe package 20-lead plastic tssop 12 3 4 5 6 7 8 9 10 top view 2019 18 17 16 15 14 13 12 11 fb v c gate fault v in sw1sw1 sw1 sw1 sw1 syncss r t shdnclkout sw2 sw2 sw2 sw2 sw2 21 gnd t jmax = 125c, ja = 38c/w, jc = 10c/w exposed pad (pin 21) is gnd, must be soldered to pcb 20 19 18 17 7 8 top view 21 gnd ufd package 20-lead (4mm 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 gate fault v in sw1sw1 sw1 r t shdnclkout sw2 sw2 sw2 fbv c sssync sw1 gndgnd sw2 t jmax = 125c, ja = 34c/w, jc = 2.7c/w exposed pad (pin 21) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3579efe#pbf lt3579efe#trpbf lt3579fe 20-lead plastic tssop C40c to 125c lt3579ife#pbf lt3579ife#trpbf lt3579fe 20-lead plastic tssop C40c to 125c lt3579eufd#pbf lt3579eufd#trpbf 3579 20-lead (4mm 5mm) plastic qfn C40c to 125c lt3579iufd#pbf lt3579iufd#trpbf 3579 20-lead (4mm 5mm) plastic qfn C40c to 125c lt3579efe-1#pbf lt3579efe-1#trpbf lt3579fe-1 20-lead plastic tssop C40c to 125c lt3579ife-1#pbf lt3579ife-1#trpbf lt3579fe-1 20-lead plastic tssop C40c to 125c lt3579eufd-1#pbf lt3579eufd-1#trpbf 35791 20-lead (4mm 5mm) plastic qfn C40c to 125c lt3579iufd-1#pbf lt3579iufd-1#trpbf 35791 20-lead (4mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts speciied with wider operating temperature ranges. *the temperature grade is identiied by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/ fault ......................................................... C0.3v to 40v fault current ..................................................... 0.5ma clkout ....................................................... C0.3v to 3v clkout current .................................................... 1ma operating junction temperature range lt3579e (notes 2, 4) ......................... C40c to 125c lt3579i (notes 2, 4) .......................... C40c to 125c storage temperature range ................... C65c to 150c downloaded from: http:///
lt3579/lt3579-1 3 35791fa for more information www.linear.com/lt3579 electrical characteristics parameter conditions min typ max units minimum input voltage l 2.3 2.5 v v in overvoltage lockout 16.2 18.7 21.2 v positive feedback voltage l 1.195 1.215 1.230 v negative feedback voltage l 3 9 16 mv positive fb pin bias current v fb =positive feedback voltage, current into pin l 80.5 83.3 85 a negative fb pin bias current v fb =negative feedback voltage, current out of pin l 81 83.3 85.5 a error amp transconductance i=10a 250 mhos error amp voltage gain 70 v/v quiescent current not switching 1.9 2.4 ma quiescent current in shutdown v shdn = 0v 0 1 a reference line regulation 2.5v v in 15v 0.01 0.05 %/v switching frequency, f osc r t = 34k? l 2.2 2.5 2.8 mhz r t = 432k? l 175 200 225 khz switching frequency in foldback compared to normal f osc 1/6 ratio switching frequency range free-running or synchronizing l 200 2500 khz sync high level for sync l 1.3 v sync low level for sync l 0.4 v sync clock pulse duty cycle v sync = 0v to 2v 20 80 % recommended minimum sync ratio f sync /f osc 3/4 minimum off-time 45 ns minimum on-time 55 ns sw1 current limit at all duty cycles (note 3) l 3.4 4.2 5.1 a sw current sharing, i sw2 /i sw1 sw1 and sw2 tied together 0.78 a/a sw1 + sw2 current limit i sw2 /i sw1 = 0.78, at all duty cycles (note 3) l 6 7.5 9.4 a switch v cesat sw1 and sw2 tied together, i sw1 + i sw2 = 5.5a 250 350 mv sw1 leakage current v sw1 = 5v 0.01 1 a sw2 leakage current v sw2 = 5v 0.01 1 a the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v in = 5v, v shdn = v in, v fault = v in unless otherwise noted. (note 2). downloaded from: http:///
lt3579/lt3579-1 4 35791fa for more information www.linear.com/lt3579 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3579e is guaranteed to meet performance speciications from 0c to 125c junction temperature. speciications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3579i is guaranteed over the full C40c to 125c operating junction temperature range. electrical characteristics the l denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. v in = 5v, v shdn = v in , v fault = v in unless otherwise noted. (note 2). parameter conditions min typ max units soft-start charge current v ss = 30mv, current flows out of ss pin l 5.7 8.7 11.3 a soft-start discharge current part in fault v ss = 2.1v, current flows into ss pin l 5.7 8.7 11.3 a soft-start high detection voltage part in f ault l 1.65 1.8 1.95 v soft-start low detection voltage part exiting fault l 30 50 85 mv shdn minimum input voltage high active mode, shdn rising active mode, shdn falling l l 1.27 1.24 1.33 1.3 1.41 1.38 v v shdn input v oltage low shutdown mode l .3 v shdn pin bias current v shdn = 3v v shdn = 1.3v v shdn = 0v 9.5 40 11.4 0 60 13.4 0.1 a a a clkout output voltage high c clkout = 50pf 1.9 2.1 2.3 v clkout output voltage low c clkout = 50pf 100 200 mv clkout duty cycle lt3579, t j = 25c 42 % lt3579-1, all t j 50 % clkout rise time c clkout = 50pf 12 ns clkout fall time c clkout = 50pf 8 ns gate pull down current v gate = 3v v gate = 80v l l 800 800 933 933 1100 1100 a a gate leakage current v gate = 50v, gate off 0.01 1 a fault output voltage low 50a into fault pin l 100 300 mv fault leakage current v fault = 40v, fault off 0.01 1 a fault input voltage low threshold l 700 750 800 mv fault input voltage high threshold l 950 1000 1050 mv note 3: current limit guaranteed by design and/or correlation to static test. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation over the speciied maximum operating junction temperature may impair device reliability. downloaded from: http:///
lt3579/lt3579-1 5 35791fa for more information www.linear.com/lt3579 typical performance characteristics switch current limit vs temperature commanded switch current vs ss positive feedback voltage oscillator frequency oscillator frequency during soft-start clkout duty cycle switch current limit switch saturation voltage switch current sharing duty cycle (%) 20 0 sw1 + sw2 current (a) 6 7 8 95 4 3 2 1 10 60 70 80 30 40 35791 g01 50 sw1 + sw2 current (a) 0 0 saturation voltage (mv) 300250 150 200100 50 350 4 5 6 7 8 1 2 35791 g02 3 v sw1 = v sw2 sw1 current (a) 0 0.0 0.1 i sw2 /i sw1 (a/a) 0.8 0.90.6 0.70.4 0.50.2 0.3 1.0 3 3.5 4 1 1.5 0.5 35791 g03 2 2.5 temperature (c) C50 0 sw1 + sw2 current (a) 8 97 6 5 4 3 2 1 10 C25 75 100 125 150 0 25 35791 g04 50 t a = 25c, unless otherwise noted. ss voltage (v) 0 0 sw1 + sw2 current (a) 95 6 7 84 3 2 1 10 0.6 0.8 1 1.2 0.2 35791 g05 0.4 temperature (c) C50 1.2 fb voltage (v) 1.225 1.22 1.215 1.21 1.205 1.23 C25 50 75 100 125 150 0 35791 g06 25 temperature (c) C50 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 frequency (mhz) 3.0 C25 100 125 150 0 25 50 35791 g07 75 r t = 432k r t = 34k fb voltage (v) 0 0 normalized oscillator frequency (f sw /f nom ) 1/6 1/5 1/4 1/3 1/2 1 0.6 0.8 1 1.2 0.2 0.4 35791 g08 boosting configurations inverting configurations temperature (c) C50 0 clkout duty cycle (%) 7060 50 40 30 20 80 C25 75 100 125 150 0 25 35791 g09 50 downloaded from: http:///
lt3579/lt3579-1 6 35791fa for more information www.linear.com/lt3579 typical performance characteristics active/lockout threshold shdn pin current shdn pin current internal uvlo v in ovlo fault input threshold clkout rise time at 1mhz gate pin current (v ss = 2.1v) gate pin current (v gate = 5v) 0 50 250 200 150 100 clkout capacitive load (pf) 0 clkout rise or fall time (ns) 5 15 20 25 5035 35791 g10 10 40 45 30 clkout fall time clkout rise time gate pin voltage (v) 0 0 gate pin current (a) 600 700 800 900550 400 300 200 100 1000 10 40 50 60 70 80 20 35791 g11 30 t a = C40c t a = 25c t a = 125c ss voltage (v) 0 0 gate pin current (a) 600 700 800 900500 400 300 200 100 1000 0.25 0.75 1 1.25 1.5 35791 g12 0.5 temperature (c) C50 1.2 shdn voltage (v) 1.32 1.34 1.36 1.38 1.3 1.281.26 1.24 1.22 1.4 C25 25 50 75 100 125 150 35791 g13 0 shdn rising shdn falling shdn voltage (v) 0 0 shdn pin current (a) 20 2515 10 5 30 0.25 0.75 1 1.25 1.5 1.75 2 35791 g14 0.5 t a = 125c t a = 25c t a = C40c shdn voltage (v) 0 0 shdn pin current (a) 200150 100 50 250 5 15 20 25 30 35 40 35791 g15 10 t a = 125c t a = 25c t a = C40c temperature (c) C50 2.1 v in voltage (v) 2.452.35 2.4 2.25 2.3 2.15 2.2 2.5 C25 25 50 75 100 125 150 35791 g16 0 temperature (c) C50 12 v in voltage (v) 2117 18 19 2015 1613 14 22 C25 25 50 75 100 125 150 35791 g17 0 temperature (c) C50 0 fault voltage (v) 0.75 1 0.5 0.25 1.25 C25 25 50 75 100 125 150 35791 g18 0 fault falling fault rising t a = 25c, unless otherwise noted. downloaded from: http:///
lt3579/lt3579-1 7 35791fa for more information www.linear.com/lt3579 pin functions gate (pin 1/pin 3): pmos gate drive pin. the gate pin is a pull-down current source, and can be used to drive the gate of an external pmos transistor for output short circuit protection or output disconnect. the gate pin current increases linearly with the ss pins voltage, with a maximum pull-down current of 933a at ss voltages exceeding 500mv. note that if the ss voltage is greater than 500mv, and the gate pin voltage is less than 2v, the gate pin looks like a 2k? impedance to ground. see the appendix for more information. fault (pin 2/pin 4): fault indication pin. this active low, bidirectional pin can either be pulled low (below 750mv) by an external source, or internally by the chip to indicate a fault. when pulled low, this pin causes the power switches to turn off, the gate pin to become high impedance, the clkout pin to become disabled, and the ss pin to go through a charge/discharge sequence. the end/absence of a fault is indicated when the voltage on this pin exceeds 1v. a pull-up resistor or some other form of pull-up network needs to exist on this pin to pull it above 1v in the absence of a fault. v in (pin 3/pin 5): input supply pin. must be locally bypassed.sw1 (pins 4 - 7/pins 6 - 10): master switch pin. this is the collector of the internal master npn power switch. sw1 is designed to handle a peak collector current of 3.4a (minimum). minimize the metal trace area connected to this pin to minimize emi. gnd (pins 8, 9, exposed pad pin 21/exposed pad pin 21): ground. must be soldered directly to local ground plane. sw2 (pins 10-13/pins 11-15): slave switch pin. this is the collector of the internal slave npn power switch. sw2 is designed to handle a peak collector current of 2.6a (minimum). minimize the metal trace area connected to this pin to minimize emi. clkout (pin 14/pin 16): clock output pin. use this pin to synchronize one or more other ics to the lt3579. this pin oscillates at the same frequency as the internal oscillator of the part or as the sync pin. clkout may also be used as a temperature monitor since the clkout pins duty cycle varies linearly with the parts junction temperature. the clkout pin signal of the lt3579-1 is 180 out of phase with the internal oscillator or sync pin, and the duty cycle is ixed at ~50%. the lt3579-1 is useful for multiphase switching regulators. shdn (pin 15/pin 17): shutdown pin. in conjunction with the uvlo (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. drive below 0.3v to disable the chip with very low quiescent current. drive above 1.33v (typical) to activate the chip and restart the soft-start sequence. do not loat this pin. rt (pin 16/pin 18): timing resistor pin. adjusts the lt3579s switching frequency. place a resistor from this pin to ground to set the frequency to a ixed free running level. do not loat this pin. sync (pin 17/pin 20): to synchronize the switching frequency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock must exceed 1.3v, and the low level must be less than 0.4v. drive this pin to less than 0.4v to revert to the internal free running clock. see the applications information section for more information. ss (pin 18/pin 19): soft-start pin. place a soft-start capacitor here. upon start-up, the ss pin will be charged by a (nominally) 250k? resistor to ~2.1v. during a fault, the ss pin will be slowly charged up and discharged as part of a timeout sequence. v c (pin 19/pin 2): error ampliier output pin. tie external com pensation network to this pin. fb (pin 20/pin 1): positive and negative feedback pin. for a boost or inverting converter, tie a resistor from the fb pin to v out according to the following equations: r fb = v out ? 1.215v 83.3a ?? ? ?? ? ; boost or sepic converter r fb = | v out | + 9mv 83.3a ?? ? ?? ? ; inverting converter (qfn/tssop) downloaded from: http:///
lt3579/lt3579-1 8 35791fa for more information www.linear.com/lt3579 block diagram figure 1. block diagram frequency foldback ramp generator comparator driverdisable ss v c r fault r gate 14.6k14.6k sr1 a3 sync clkout n ss shdn c out1 sw1 sw2 fb 15.4m r s 12m gnd r t rt r c c c v c driver v in c in sync block uvlo r s q 35791 bd C + a4 q2 +C td ~ 30ns vbe ? 0.9 C+ C+ 1.17v45mv fb adjustable oscillator ? + ? + a1 c ss 1.33v +? +? +? 250k 2.1v 1.8v 50mv soft- start startup & fault logic c out v out v in m 1 l1 gate optional fault 933a ?+ +? +? +? +? +? die temp 165c v in 750mv sw1i sw1 42v (min)42v (min) 3.4a (min) sw2 ? + a2 1.215v reference 16.2v d1 r fb q1 **** ** sw overvoltage protection is not guaranteed to protect the lt3579/lt3579-1 during sw overvoltage events. downloaded from: http:///
lt3579/lt3579-1 9 35791fa for more information www.linear.com/lt3579 shdn < 1.33v or v in < 2.3v shdn > 1.33v and v in > 2.3v fault detected ? ss charges up ? igate off ? fault pulled low internally by lt3579 ? switcher disabled? clkout disabled ss < 50mv if |v out | drops causing: fb < 1.17v (boost) or fb > 45mv (inverting) ss > 1.8v and no fault1 conditions still detected ss < 50mv fault1 fault1 fault1 fault1 fault1 fault1 fault2 fault > 1.0v fault1 = over voltage protection on v in (v in > 16.2v (min)) over temperature (t junction > 165c (typ)) over current on sw1 (i sw1 > 3.4a (min)) over voltage protection on sw1 (v sw1 > 42v (min)) over voltage protection on sw1 (v sw2 > 42v (min)) fault2 = fault pulled low externally ( fault < 0.75v) chip off ? all switches disabled? i gate off ? faults cleared initialize ? ss pulled low normal mode ? normal operation ? clkout enabled when ss > 1.8v sample mode ? q1 & q2 switches forced on every cycle for at least minimum on-time ? i gate fully activated when ss > 500mv soft start ? i gate enabled ? ss charges up? switcher enabled post fault delay ? ss slowly discharges local fault over ? internal fault pulldown released by lt3579 ? ss continues discharging to gnd 35791 sd state diagram figure 2. state diagram downloaded from: http:///
lt3579/lt3579-1 10 35791fa for more information www.linear.com/lt3579 operation operation ? overview the lt3579 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. the parts undervoltage lockout (uvlo) function, together with soft-start and frequency foldback, offers a controlled means of starting up. fault features are incorporated in the lt3579 to aid in the detection of output shorts, over- voltage, and overtemperature conditions. refer to the block diagram (figure 1) and the state diagram (figure 2) for the following description of the parts operation. operation ? start-up several functions are provided to enable a very clean start-up for the lt3579. precise turn-on voltage the shdn pin compares to an internal voltage reference to give a precise turn on voltage level. taking the shdn pin above 1.33v (typical) enables the part. taking the shdn pin below 0.3v shuts down the chip, resulting in extremely low quiescent current. the shdn pin has 30mv of hysteresis to protect against glitches and slow ramping. undervoltage-lockout (uvlo) the shdn pin can also be used to create a conigurable uvlo. the uvlo function sets the turn on/off of the lt3579 at a desired input voltage (vin uvlo ). figure 3 shows how a resistor divider (or single resistor) from v in to the shdn pin can be used to set vin uvlo . r uvlo2 is optional. it may be left out, in which case set it to ininite in the equation below. for increased accuracy, set r uvlo2 10k?. pick r uvlo1 as follows: r uvlo1 = vin uvlo ? 1.33v 1.33v r uvlo2 ?? ?? ?? ?? + 11.6a r uvlo2 (optional) 1.33v r uvlo1 35791 f03 v in v in active/ lockout gnd 11.6a at 1.33v C + shdn figure 3. con?gurable uvlo the lt3579 also has internal uvlo circuitry that disables the chip when v in < 2.3v (typical). soft-start of switch current the soft-start circuitry provides for a gradual ramp-up of the switch current (refer to commanded switch current vs. ss in typical performance characteristics). when the part is brought out of shutdown, the external ss capacitor is irst discharged which resets the states of the logic circuits in the chip. then an integrated 250k resistor pulls the ss pin to ~1.8v at a ramp rate set by the external capacitor connected to the pin. once ss gets to 1.8v, the clkout pin is enabled, and an internal regulator pulls the pin up quickly to ~2.1v. typical values for the external soft-start capacitor range from 100nf to 1f. soft-start of external pmos (if used) the soft-start circuitry also gradually ramps up the gate pin pull-down current which allows an external pmos to slowly turn on (m1 in block diagram). the gate pin current increases linearly with ss voltage, with a maximum current of 933a when the ss voltage gets above 500mv. note that if the gate pin voltage is less than 2v for ss voltages exceeding 500mv, then the gate pin impedance to ground is 2k?. the soft turn on of the external pmos helps limit inrush current at start-up, making hot plugs of the lt3579 feasible and safe. downloaded from: http:///
lt3579/lt3579-1 11 35791fa for more information www.linear.com/lt3579 sample mode sample mode is the mechanism used by the lt3579 to aid in the detection of output shorts. it refers to a state of the lt3579 where the master and slave power switches (q1 and q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to sample the inductor current. if the sampled current through q1 exceeds the master switch current limit of 3.4a (minimum), the lt3579 triggers an overcurrent fault internally (see operation-fault section for details). sample mode exists when fb is out of regulation by more than 3.7% or 45mv < fb < 1.17v (typical). the lt3579s power switches are designed to handle a total peak current of 6a (minimum). frequency foldback the frequency foldback circuit reduces the switching frequency when 350mv < fb < 900mv (typical). this feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current during start-up. when the fb voltage is pulled outside of this range, the switching frequency returns to normal. note that the peak inductor current at start-up is a function of many variables including load proile, output capacitance, target v out , v in , switching frequency, etc. test the application?s performance at start-up to ensure that the peak inductor current does not exceed the minimum current limit. operation ? regulation the following description of the lt3579s operation assumes the fb voltage is close enough to its regulation target so that the part is not in sample mode. use the block diagram as a reference when stepping through the following description of the lt3579 operating in regulation. at the start of each oscillator cycle, the sr latch (sr1) is set, which turns on the power switches q1 and q2. the collector current through the master switch, q1, is ~1.3 times the collector current through the slave switch, q2, when the collectors of the two switches are tied together. q1s emitter current lows through a current operation sense resistor (r s ) generating a voltage proportional to the total switch current. this voltage (ampliied by a4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator a3. when the voltage on the positive input of a3 exceeds the voltage on the negative input, the sr latch is reset, turning off the master and slave power switches. the voltage on the negative input of a3 (v c pin) is set by a1 (or a2), which is simply an ampliied difference between the fb pin voltage and the reference voltage (1.215v if the lt3579 is conigured as a boost converter, or 9mv if conigured as an inverting converter). in this manner, the error amplifer sets the correct peak current level to maintain output regulation. as long as the part is not in fault (see operation C fault section) and the ss pin exceeds 1.8v, the lt3579 drives its clkout pin at the frequency set by the rt pin or the sync pin. the clkout pin can synchronize other compatible switching regulator ics (including additional lt3579s) with the lt3579. additionally, the duty cycle of clkout varies linearly with the parts junction temperature and may be used as a temperature monitor. the clkout signal on the lt3579-1 is ~180 out of phase with the internal oscillator and has a ixed duty cycle of ~50%. operation ? fault the lt3579s fault pin is an active low, bidirectional pin (refer to block diagram) that pulls low to indicate a fault. each of the following events can trigger a fault in the lt3579: a. fault1 events: 1. sw overcurrent a. i sw1 > 3.4a (minimum) b. (i sw1 + i sw2 ) > 6a (minimum) 2. v in voltage > 16.2v (minimum) 3. sw1 voltage and/or sw2 voltage > 42v (minimum) 4. die temperature > 165c b. fault2 events: 1. pulling the fault pin low externally downloaded from: http:///
lt3579/lt3579-1 12 35791fa for more information www.linear.com/lt3579 operation when a fault is detected, in addition to the fault pin being pulled low internally, the lt3579 also disables its clkout pin, turns off its power switches, and the gate pin becomes high impedance (refer to the state diagram). the external pmos, m1, turns off when the gate of m1 is pulled up to its source by the external r gate resistor (see block diagram) with the external pmos turned off, the power path from v in to v out is cut off, protecting power components downstream.at the same time, a timeout sequence commences where the ss pin is charged up to 1.8v (the ss pin will continue charging up to ~2.1v and be held there in the case of a fault1 event still existing), and then discharged to 50mv. this timeout period relieves the part, the pmos, and other downstream power components from electrical and thermal stress for a minimum amount of time as set by the voltage ramp rate on the ss pin. in the absence of faults, the fault pin is pulled high by the external r fault resistor (typically 100k). figures 4 and 5 show the events that accompany the detection of an output short on the lt3579. figure 4. output short circuit protection of the lt3579 10s/div v out 10v/div il 5a/div fault 5v/div clkout 2v/div 35791 f04 50ms/div ss 2v/div il 5a/div fault 5v/div gate 5v/div 35791 f05 figure 5. continuous output short showing fault timeout cycle downloaded from: http:///
lt3579/lt3579-1 13 35791fa for more information www.linear.com/lt3579 applications information figure 6. boost converter ? the component values given are typical values for a 1mhz, 5v to 12v boost boost converter component selection optional v in 5v c in 22f r t 86.6k c out1 10f r gate 6.3k r c 8k c c 2.2nf c f 47pf c ss 0.1f r fb 130k v out 12v1.7a v in c out 10f l1 2.2h d1 30v, 4a sw1 sw2 gate v in rt v c fault shdn fb ss gnd sync clkout lt3579 35791 f06 100k200k m 1 the lt3579 can be conigured as a boost converter as in figure 6. this topology allows for positive output voltages that are higher than the input voltage. an external pmos (optional) driven by the gate pin of the lt3579 can achieve input or output disconnect during a fault event. a single feedback resistor sets the output voltage. for output voltages higher than 40v, see the charge pump topology in the charge pump aided regulators section. table 1 is a step-by-step set of equations to calculate component values for the lt3579 when operating as a boost converter. input parameters are input and output voltage, and switching frequency (v in , v out and f osc respectively). refer to the appendix for further information on the design equations presented in table 1. variable de?nitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum output current i ripple = inductor ripple current r dson_pmos = r dson of external pmos (set to 0 if not using pmos) table 1. boost design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below. step 2: dc dc ? v out ? v in + 0.5v v out + 0.5v ? 0.27v step 3: l1 l typ = v in ? 0.27v ( ) ? dc f osc ? 1.8a l min = v in ? 0.27v ( ) ? 2 ? dc ? 1 ( ) 4a ? f osc ? 1 ? dc ( ) l max = v in ? 0.27v ( ) ? dc f osc ? 0.5a (1)(2) (3) ? solve equations 1, 2, and 3 for a range of l1 values.? the minimum of the l1 value range is the higher of l typ and l min . ? the maximum of the l1 value range is l max . step 4: i ripple i ripple = v in ? 0.27v ( ) ? dc f osc ? l1 step 5: i out i out = 6a ? i ripple 2 ?? ? ?? ? ? 1 ? dc ( ) step 6: d1 v r > v out ; i avg > i out step 7: c out, c out1 c out = c out1 = i out ? dc f osc ? 0.01?v out C0.5?i out ?r dson_pmos ( ) step 8: c in c in = c pwr + c vin c in = i ripple 8 ? f osc ? 0.005 ? v in + 6a ? dc 40 ? f osc ? 0.005 ? v in step 9: r fb r fb = v out C 1.215v 83.3a step 10: r t r t = 87.6 f osc C 1; f osc in mhz and r t in k ? step 11: pmos only needed for input or output disconnect. see pmos selection in the appendix for information on sizing the pmos and the biasing resistor, r gate . note: the maximum design target for peak switch current is 6a and is used in this table. the ?nal values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. downloaded from: http:///
lt3579/lt3579-1 14 35791fa for more information www.linear.com/lt3579 applications information figure 7. sepic converter ? the component values given are typical values for a 1mhz, 9v?16v to 12v sepic topology using coupled inductors sepic converter component selection ? coupled or un-coupled inductors the lt3579 can also be conigured as a sepic as in figure 7. this topology allows for positive output voltages that are lower, equal, or higher than the input voltage. output disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output due to capacitor c1. this implies that a pmos controlled by the gate pin is not required in the power path. table 2 is a step-by-step set of equations to calculate component values for the lt3579 when operating as a sepic converter using coupled inductors. input parameters are input and output voltage, and switching frequency (v in , v out and f osc respectively). refer to the appendix for further information on the design equations presented in table 2. variable de?nitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum output current i ripple = inductor ripple current table 2. sepic design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below. step 2: dc d c ? v out + 0.5v v in + v out + 0.5v ? 0.27v step 3: l l typ = v in ? 0.27v ( ) ? dc f osc ? 1.8a l min = v in ? 0.27v ( ) ? 2 ? dc ? 1 ( ) 4a ? f osc ? 1 ? dc ( ) l max = v in ? 0.27v ( ) ? dc f osc ? 0.5a (1)(2) (3) ? solve equations 1, 2, and 3 for a range of l values.? the minimum of the l value range is the higher of l typ and l min . ? the maximum of the l value range is l max . ? l = l1 = l2 for coupled inductors.? l = l1 || l2 for uncoupled inductors. step 4: i ripple i ripple = v in ? 0.27v ( ) ? dc f osc ? l step 5: i out i out = 6a ? i ripple 2 ?? ? ?? ? ? 1 ? dc ( ) step 6: d1 v r > v in + v out ; i avg > i out step 7: c1 4.7f (typical) ; v rating > v in step 8: c out c out = i out ? dc f osc ? 0.005 ?v out step 9: c pwr c pwr = i ripple 8 ? f osc ? 0.005 ? v in step 10: c vin c vin = 6a ? dc 40 ? f osc ? 0.005 ? v in step 11: r fb r fb = v out C 1.215v 83.3a step 12: r t r t = 87.6 f osc C 1; f osc in mhz and r t in k ? note: the maximum design target for peak switch current is 6a and is used in this table. the ?nal values for c out , c pwr , and c vin may deviate from the above equations in order to obtain desired load transient performance for a particular application. v pwr 9v to 16v r t 86.6k 100k c out 10f 3 c pwr 4.7f r fb 130k c f 47pf c ss 0.22f c vin 4.7f l1 6.8h d1 60v, 3a c1 4.7f sw1 sw2 gate v in rt v c c c 2.2nf r c 9.53k fault shdn fb ss gnd sync clkout lt3579 35791 f07 v out 12v1.6a (v pwr >9v) 1.9a (v pwr >12v) l26.8h v in 3.3v to 5v downloaded from: http:///
lt3579/lt3579-1 15 35791fa for more information www.linear.com/lt3579 applications information figure 8. dual inductor inverting converter ? the component values given are typical values for a 1.2mhz, 5v to ?12v inverting topology using coupled inductors dual inductor inverting converter component selection ? coupled or un-coupled inductors due to its unique fb pin, the lt3579 can work in a dual inductor inverting coniguration as in figure 8. changing the connections of l2 and the schottky diode in the sepic topology, results in generating negative output voltages. this solution results in very low output voltage ripple due to inductor l2 in series with the output. output disconnect is inherently built into this topology due to the capacitor c1. table 3 is a step-by-step set of equations to calculate component values for the lt3579 when operating as a dual inductor inverting converter using coupled inductors. input parameters are input and output voltage, and switching frequency (v in , v out and f osc respectively). refer to the appendix for further information on the design equations presented in table 3. variable de?nitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum output current i ripple = inductor ripple current table 3. dual inductor inverting design equations parameters/equations step 1: inputs pick v in , v out , and f osc to calculate equations below. step 2: dc dc ? | v out | + 0.5v v in + | v out | + 0.5v ? 0.27v step 3: l l typ = v in ? 0.27v ( ) ? dc f osc ? 1.8a l min = v in ? 0.27v ( ) ? 2 ? dc ? 1 ( ) 4a ? f osc ? 1 ? dc ( ) l max = v in ? 0.27v ( ) ? dc f osc ? 0.5a (1)(2) (3) ? solve equations 1, 2, and 3 for a range of l values.? the minimum of the l value range is the higher of l typ and l min . ? the maximum of the l value range is l max . ? l = l1 = l2 for coupled inductors.? l = l1 || l2 for uncoupled inductors. step 4: i ripple i ripple = v in ? 0.27v ( ) ? dc f osc ? l step 5: i out i out = 6a ? i ripple 2 ?? ? ?? ? ? 1 ? dc ( ) step 6: d1 v r > v in + | v out | ; i avg > i out step 7: c1 4.7f (typical) ; v rating > v in + | v out | step 8: c out c out = i ripple 8 ? f osc ? 0.005 ? | v out | step 9: c in c in = c pwr + c vin c in = i ripple 8 ? f osc ? 0.005 ? v in + 6a ? dc 40 ? f osc ? 0.005 ? v in step 10: r fb r fb = | v out | + 9mv 83.3a step 11: r t r t = 87.6 f osc C 1; f osc in mhz and r t in k ? note: the maximum design target for peak switch current is 6a and is used in this table. the ?nal values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. v in 5v r t 72k 100k c out 10f 2 r fb 144k c f 27pf l1 3.3h l2 3.3h d1 30v, 2a c1 4.7f sw1 sw2 v in rt v c c c 1nf r c 20k fault shdn fb clkout ss sync gnd gate lt3579 35791 f08 v out C12v 1.2a c ss 0.22f c in 22f downloaded from: http:///
lt3579/lt3579-1 16 35791fa for more information www.linear.com/lt3579 applications information layout guidelines for boost, sepic, and dual inductor inverting topologies general layout guidelines ? to optimize thermal performance, solder the exposed ground pad of the lt3579 to the ground plane with multiple vias around the pad connecting to additional ground planes. ? a ground plane should be used under the switcher circuitry to prevent interplane coupling and overall noise. ? high speed switching path (see speciic topology below for more information) must be kept as short as possible. ? the v c , fb, and rt components should be placed as close to the lt3579 as possible, while being as far away as practically possible from the switch node. the ground for these components should be separated from the switch current path. ? place the bypass capacitor for the v in pin (c vin ) as close as possible to the lt3579. ? place the bypass capacitor for the inductor (c pwr ) as close as possible to the inductor. ? bypass capacitors, c pwr and c vin , may be combined into a single bypass capacitor, c in , if the input side of the inductor can be close to the v in pin of the lt3579. ? the load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. boost topology speci?c layout guidelines ? keep length of loop (high speed switching path) governing switch, diode d1, output capacitor c out , and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. sepic topology speci?c layout guidelines ? keep length of loop (high speed switching path) governing switch, lying capacitor c1, diode d1, output capacitor c out , and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. figure 9. suggested component placement for boost topology in fe20 package aC return c in ground directly to lt3579 exposed pad pin 21. it is advised to not combine c in ground with gnd except at the exposed pad. bC return c out and c out1 ground directly to lt3579 exposed pad pin 21. it is advised to not combine c out and c out1 ground with gnd except at the exposed pad. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 gnd c in v in r gate C+ + C v out c out c out1 a b sync clkout shdn vias to ground plane required to improve thermal performance 35791 f08 m1 d1 d2 l1 downloaded from: http:///
lt3579/lt3579-1 17 35791fa for more information www.linear.com/lt3579 the heat generated within the package. this can be accomplished by taking advantage of the thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. power & thermal calculations power dissipation in the lt3579 chip comes from four primary sources: switch i 2 r loss, npn base drive loss (ac), npn base drive loss (dc), and additional v in pin current. these formulas assume continuous mode operation, so they should not be used for calculating thermal losses or eficiency in discontinuous mode or at light load currents. inverting topology speci?c layout guidelines ? keep ground return path from the cathode of d1 (to chip) separated from output capacitor c out s ground return path (to chip) in order to minimize switching noise coupling into the output. notice the separate ground return for d1s cathode in figure 11. ? keep length of loop (high speed switching path) governing switch, lying capacitor c1, diode d1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. thermal considerations for the lt3579 to deliver its full output power, it is imp- erative that a good thermal path be provided to dissipate aC return c in and l2 ground directly to lt3579 exposed pad pin 21. it is advised to not combine c in and l2 ground with gnd except at the exposed pad. bC return c out ground directly to lt3579 exposed pad pin 21. it is advised to not combine c out ground with gnd except at the exposed pad. l1, l2 Cmost coupled inductor manufacturers use cross pinout for improved performance. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 gnd c in v in C+ + C v out c out a b sync clkout shdn vias to ground plane required to improvethermal performance 35791 f10 l1 l2 d1 c1 figure 10. suggested component placement for sepic topology in fe20 package applications information downloaded from: http:///
lt3579/lt3579-1 18 35791fa for more information www.linear.com/lt3579 applications information figure 11. suggested component placement for inverting topology in fe20 package. note separate ground path for d1?s cathode 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 gnd c in v in C+ Cv out gnd c out ac b sync clkout shdn vias to ground plane required to improvethermal performance aC return c in ground directly to lt3579 exposed pad pin 21. it is advised to not combine c in ground with gnd except at the exposed pad. bC return c out ground directly to lt3579 exposed pad pin 21. it is advised to not combine c out ground with gnd except at the exposed pad. cC return d1 ground directly to lt3579 exposed pad pin 21. it is advised to not combine d1 ground with gnd except at the exposed pad. l1, l2 C most coupled inductor manufacturers use cross pinout for improved performance. 35791 f11 c1 d1 l1 l2 downloaded from: http:///
lt3579/lt3579-1 19 35791fa for more information www.linear.com/lt3579 table 4. boost power calculations example with v in = 5v, v out = 12v, i out = 1.5a, f osc = 1mhz, v d = 0.5v, v cesat = 0.185v definition of variables equations design example value dc = switch duty cycle dc = v out C v in + v d v out + v d C v cesat dc = 12v C 5v + 0.5v 12v + 0.5v C .185v dc = 60.9% i in = average input current = power conversion eficiency (typically 90% at high currents) i in = v out ? i out v in ? i in = 12v ? 1.5a 5v ? 0.9 i in = 4a p sw = switch i 2 r loss r sw = switch resistance (typically 45m combined sw1 and sw2) p sw = dc ? i in 2 ? r sw p sw = 0.609 ? (4a) 2 ? 45m ? p sw = 438mw p bac = base drive loss (ac) p bac = 13ns ? i in ? v out ? f osc p bac = 13ns ? 4a ? 12v ? 1mhz p bac = 624mw p bdc = base drive loss (dc) p bdc = v in ? i in ? dc 40 p bdc = 5v ? 4a ? 0.609 40 p bdc = 305mw p inp = input power loss p inp = 14ma ? v in p inp = 14ma ? 5v p inp = 70mw p total = 1.437w applications information the following example calculates the power dissipation in the lt3579 for a particular boost application: (v in = 5v, v out = 12v, i out = 1.5a, f osc = 1mhz, v d = 0.5v, v cesat = 0.185v). to calculate die junction temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: t j = t a + ja ? p total where t j =die junction temperature, t a =ambient tem - perature, p total is the inal result from the calculations shown in table 4, and ja is the thermal resistance from the silicon junction to the ambient air. downloaded from: http:///
lt3579/lt3579-1 20 35791fa for more information www.linear.com/lt3579 applications information thermal lockouta fault condition occurs when the die temperature exceeds ~165c (see operation C fault section), and the part goes into thermal lockout. the fault condition ceases when the die temperature drops by ~5c (nominal). switching frequency there are several considerations in selecting the operating frequency of the converter. the irst is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. for example, in products incorporating rf communications, the 455khz if frequency is sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1mhz and in that case a 1.5mhz switching converter frequency may be employed. the second consideration is the physical size of the converter. as the operating frequency goes up, the inductor and ilter capacitors go down in value and size. the tradeoff is eficiency, since the switching losses due to npn base charge (see thermal considerations), schottky diode charge, and other capacitive loss terms increase proportionally with frequency. oscillator timing resistor (r t ) the operating frequency of the lt3579 can be set by the internal free-running oscillator. when the sync pin is driven low (< 0.4v), the frequency of operation is set by a resistor from the rt pin to ground. an internally trimmed timing capacitor resides inside the ic. the oscillator frequency is calculated using the following formula: f osc = 87.6 r t + 1 the published (http://www.linear.com/designtools/packag - ing/linear_technology_thermal_resistance_table.pdf) ja value is 38c/w for the tssop exposed pad package and 34c/w for the 4mm 5mm qfn package. in practice, lower ja values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the layout guidelines section. for instance, a ja value of ~22c/w was consistently achieved for both tssop and qfn packages of the lt3579 (at v in = 5v, v out = 12v, i out = 1.7a, f osc = 1mhz) when board layout was optimized as per the suggestions in the layout guidelines section. junction temperature measurement the duty cycle of the clkout signal on the lt3579 is lin early proportional to die junction temperature, t j (the clkout duty cycle on the lt3579-1 is ixed at ~50%). to get an accurate reading, measure the duty cycle of the clkout signal and use the following equation to approximate the junction temperature: t j = dc clkout C 35% 0.3% where dc clkout is the clkout duty cycle in % and t j is the die junction temperature in c. although the absolute die temperature can deviate from the above equation by 15c, the relationship between change in clkout duty cycle and change in die temperature is well deined. a 3% increase in clkout duty cycle corresponds to ~10c increase in die temperature: note that the clkout pin is only meant to drive capacitive loads up to 50pf. downloaded from: http:///
lt3579/lt3579-1 21 35791fa for more information www.linear.com/lt3579 3.3h 10f 10f 200k v out 18v1a v out 12v1.7a v in 5v 35791 f12 sw1 sw2 gate fb v c ss gnd sync clkout v in rt shdn fault lt3579 slave 10f 2 10f 3 8k 100k110k 3.3nf 0.1f 68pf 47pf 4.7f 4.7f 86.6k 86.6k 2.2h 10k sw1 sw2 gate clkout v c ss gnd sync fb v in rt fault shdn lt3579 master 2.2nf 8k 130k 0.1f figure 12. synchronize multiple lt3579s. the external pmos disconnects the input from both power paths during fault events clock synchronization of additional regulators the clkout pin of the lt3579 can synchronize additional switching regulators and/or additional lt3579s as shown in figure 12. applications information where f osc is in mhz and r t is in k. conversely, r t (in k) can be calculated from the desired frequency (in mhz) using: r t = 87.6 f osc C 1 clock synchronization an external source can set the operating frequency of the lt3579 by providing a digital clock signal into the sync pin (r t resistor still required). the lt3579 will operate at the sync clock frequency. the lt3579 will revert to its internal free-running oscillator clock when the sync pin is driven below 0.4v for a few free-running clock periods. driving sync high for an extended period of time effectively stops the operating clock and prevents latch sr1 from becoming set (see block diagram). as a result, the switching operation of the lt3579 will stop and the clkout pin will be held at ground. the duty cycle of the sync signal must be between 20% and 80% for proper operation. also, the frequency of the sync signal must meet the following two criteria: 1. sync may not toggle outside the frequency range of 200khz-2.5mhz unless it is stopped below 0.4v to enable the free-running oscillator. 2. the sync frequency can always be higher than the free-running oscillator frequency (as set by the r t resistor), f osc , but should not be less than 25% below f osc . downloaded from: http:///
lt3579/lt3579-1 22 35791fa for more information www.linear.com/lt3579 applications information the frequency of the master lt3579 is set by the external r t resistor. the sync pin of the slave lt3579 is driven by the clkout pin of the master lt3579. note that the rt pin of the slave lt3579 must have a resistor tied to ground. it takes a few clock cycles for the clkout signal to begin oscillating, and its preferable for all lt3579s to have the same internal free-running frequency. therefore, in general, use the same value r t resistor for all of the synchronized lt3579s. also, the fault pins can be tied together so that a fault condition from one lt3579 causes all of the lt3579s to enter fault, until the fault condition disappears. 2-phase converters using lt3579-1 the clkout pin on the lt3579-1 is ~180 out of phase with the internal oscillator, which allows two lt3579-1s to operate in parallel for a high current, high power output. the advantage of multiphase converters is that the ripple current lowing into the output node is divided by the number of phases or ics used to generate the output voltage. the v in , shdn , fault , fb, and v c pins of all the lt3579-1s should be connected together. figure 13 shows a typical application of a 2-phase 12v to 24v boost with output disconnect. use the following equations to calculate the fb resistor for 2-phase converters: r fb = v out C 1.215v 2 ? 83.3a ?? ? ?? ? ; boost or sepic multiphase converter r fb = | v out | + 9mv 2 ? 83.3a ?? ? ?? ? ; inverting multiphase converter 4.7h 4.7h v pwr 12v v in 5v v out 24v 3.7a, 89w v out1 v out1 v pwr 10f 4.7f 10f 4.7f 2 0.22f 4.7f 4.7f 2 137k 35791 f13 sw1 sw2 v in clkout gate v c ss gnd fb fault sync shdnrt lt3579-1 master sw1 sw2 v in clkout gate v c ss gnd fb fault sync shdnrt lt3579-1 slave 86.6k 6.4k 7k 2.2nf 47pf 0.22f 5k 86.6k 21.5k 500k 100k 4.7f 2 figure 13. 2-phase converters using lt3579-1 note that the clkout pin on the lt3579-1 runs at a ixed duty cycle of ~50%. if monitoring the die temperature is desired, the slave ic can be a lt3579. it is possible to use the lt3579-1 in a multiphase converter of more than 2 phases. consult the ltc applications engineering department for more information. downloaded from: http:///
lt3579/lt3579-1 23 35791fa for more information www.linear.com/lt3579 applications information charge pump aided regulators designing charge pumps with the lt3579 can offer eficient solutions with fewer components than traditional circuits because of the master/slave switch coniguration on the ic. the current in the master switch (sw1) is sensed by the current comparator (a4 in block diagram), but the current in the slave switch (sw2) is not. note that the slave switch, sw2, operates in phase with sw1. this method of operation by the master/slave switches can offer the following beneits to charge pump designs: ? the slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes when the lying capacitors charge up. since this current spike lows through sw2, it does not affect the operation of the current comparator (a4 in block diagram). ? the master switch, immune from the capacitor current spike, can sense the inductor current more accurately. ? since the slave switch can sustain large current spikes, the diodes that feed current into the lying capacitors do not need current limiting resistors, leading to eficiency and thermal improvements. high v out charge pump topology the lt3579 can be used in a charge-pump topology (refer to figure 16), multiplying the output of an inductive boost converter. the master switch (sw1) can be used to drive the inductive boost converter, while the slave switch (sw2) can be used to drive one or more charge pump stages. this topology is useful for high voltage applications including vfd bias supplies. single inductor inverting topology if there is a need to use just 1 inductor to generate a negative output voltage whose magnitude is greater than v in , the single inductor inverting topology (shown in figure 15) can be used. since the master and slave switches are isolated by an external schottky diode, the current spike through c1 will low through the slave switch, thereby preventing the current comparator (a4 in block diagram) from falsely tripping. output disconnect is inherently built into the single inductor topology . hot plugthe high inrush current associated with hot-plugging v in can be largely rejected with the use of an external pmos. a simple hot-plug controller can be designed by connecting an external pmos in series with v in , with the gate of the pmos being driven by the gate pin of the lt3579. since the gate pin pull-down current is linearly proportional to the ss voltage, and the ss charge up time is relatively slow, the gate pin pull-down current will increase gradually, thereby turning on the external pmos slowly. controlled in this manner, the pmos acts as an input current limiter when v in hot-plugs or ramps up sharply. likewise, when the pmos is connected in series with the output, inrush currents into the output capacitor can be limited during a hot-plug event. to illustrate this, the circuit in figure 6 was re-conigured by adding a large 1500f capacitor to the output. an 18 resistive load was used and a 2.2f capacitor was placed on ss. figure 14 shows the result of hot-plugging this re-conigured circuit. the inductor current is well behaved and v out comes up once v in settles out. downloaded from: http:///
lt3579/lt3579-1 24 35791fa for more information www.linear.com/lt3579 applications information figure 14. v in hot-plug control. inrush current is well controlled 1s/div v in 5v/div v out 10v/div i l 5a/div ss 1v/div 35791 f14 v in 12v v out2 100v 200ma v out1 67v 100ma 10h 4.7f4.7f 6.8f 4.7f4.7f 6.8f 100k 10f sw1 sw2 v in fb clkout v c ss gnd gate fault sync rt shdn lt3579 35791 f16 383k 6.5k 34k 470pf 2.2f 27pf 86.6k 536k v in figure 16. high v out charge pump topology v in c in c ss c f c c r c Cv out sw1 sw2 v in fb clkout v c ss gnd gate shdn fault sync rt lt3579 c out 100k l1 d1 d2 d3 c1 r fb 35791 f15 r t figure 15. single inductor inverting topology downloaded from: http:///
lt3579/lt3579-1 25 35791fa for more information www.linear.com/lt3579 appendix setting the output voltage the output voltage is set by connecting a resistor (r fb ) from v out to the fb pin. r fb is determined from the following equation: r fb = | v out C v fb | 83.3a where v fb is 1.215v (typical) for non-inverting topologies (i.e. boost and sepic regulators) and 9mv (typical) for inverting topologies (see electrical characteristics). power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the power npns (q1 and q2 in the block diagram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = t p C minofftime ( ) t p ? 100% where t p is the clock period and minofftime (found in the electrical characteristics) is typically 45ns. conversely, the power npns (q1 and q2 in the block diagram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum time (minontime) when in regulation. this minontime governs the minimum allowable duty cycle given by: dc min = minontime ( ) t p ? 100% where t p is the clock period and minontime (found in the electrical characteristics) is typically 55ns. the application should be designed such that the operating duty cycle is between dc min and dc max . duty cycle equations for several common topologies are given below where v d is the diode forward voltage drop and v cesat is typically 250mv at 5.5a for a combined sw1 and sw2 current. for the boost topology (see figure 6): dc boost ? v out C v in + v d v out + v d C v cesat for the sepic or dual inductor inverting topology (see figures 7 and 8): dc sepic _& _invert ? v d + | v out | v in + | v d | + v out ? v cesat for the single inductor inverting topology (see figure 14): dc si_invert ? | v out | ? v in + v cesat + 3 ? v d | v out | + 3 ? v d the lt3579 can be used in conigurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. inductor selection the high frequency operation of the lt3579 allows for the use of small surface mount inductors. for high eficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. also to improve eficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr (copper-wire resistance) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturating. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one half of the total switch current. multilayer chokes or chip inductors usually do not have enough core volume to support peak inductor currents in the 4a to 7a range. to minimize radiated noise, use a toroidal or shielded inductor. see table 5 for a list of inductor manufacturers. downloaded from: http:///
lt3579/lt3579-1 26 35791fa for more information www.linear.com/lt3579 appendix table 5. inductor manufacturers vishay ihlp-2020bz-01 and ihlp-2525cz-01 series www.vishay.com coilcraft xlp, mlc and mss series www.coilcraft.com cooper bussmann drq125 and drq127 series www.cooperbussmann. com sumida cdrh series www.sumida.com tdk rlf and slf series www.tdk.com wrth we-pd, we-pdf, we-hc and we-dd series www.we-online.com minimum inductance although there can be a tradeoff with eficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are three conditions that limit the minimum inductance; (1) providing adequate load current, (2) avoidance of subharmonic oscillation, and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. adequate load current small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. in order to provide adequate load current, l should be at least: l boost > dc ? v in ? v cesat ( ) 2 ? f osc ? i pk ? v out ? i out v in ? ?? ? ?? ? or l dual > dc ? v in ? v cesat ( ) 2 ? f osc ? i pk ? |v out | ? i out v in ? ? i out ?? ? ?? ? boost topology sepic or inverting topologies where: l boost = l 1 for boost topologies (see figure 6) l dual = l1 = l2 for coupled dual inductor topologies (see figures 7 and 8) l dual = l1 || l2 for uncoupled dual inductor topologies (see figures 7 and 8) dc = switch duty cycle (see power switch duty cycle section in appendix) i pk = maximum peak switch current; should not exceed 6a for a combined sw1 + sw2 current or 3.4a of sw1 current (see electrical characteristics section.) = power conversion eficiency (typically 90% for boost and 85% for dual inductor topologies at high currents) f osc = switching frequency i out = maximum output current negative values of l boost or l dual indicate that the output load current, i out , exceeds the switch current limit capability of the lt3579. avoiding sub-harmonic oscillations the lt3579s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: l min = v in ? v cesat ( ) ? 2 ? dc ? 1 ( ) 4a ? f osc ? 1 ? dc ( ) where: l min = l1 for boost topologies (see figure 6) l min = l1 = l2 for coupled dual inductor topologies (see figures 7 and 8) l min = l1 || l2 for uncoupled dual inductor topologies (see figures 7 and 8) downloaded from: http:///
lt3579/lt3579-1 27 35791fa for more information www.linear.com/lt3579 appendix maximum inductance excessive inductance can reduce ripple current to levels that are dificult for the current comparator (a4 in the block diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max = v in ? v cesat ( ) ? dc f osc ? 0.5a where: l max = l1 for boost topologies (see figure 6) l max = l1 = l2 for coupled dual inductor topologies (see figures 7 and 8) l max = l1 || l2 for uncoupled dual inductor topologies (see figures 7 and 8) inductor current rating the inductor(s) must have a rating greater than its (their) peak operating current to prevent inductor saturation, which would result in catastrophic failure and eficiency losses. the maximum inductor current (considering start-up and steady-state conditions) is given by: i l _ peak = i lim + v in ? t min _ prop l where: i l_peak = peak inductor current in l1 for a boost topology, or the sum of the peak inductor currents in l1 and l2 for dual inductor topologies. i lim = for hard-saturation inductors, 9.4a with sw1 and sw2 tied together, or 5.1a with just sw1 used. for soft-saturation inductors, 6a with sw1 and sw2 tied together, or 3.4a with just sw1 used. t min_prop = 100ns (propagation delay through the current feedback loop). note that these equations offer conservative results for the required inductor current ratings. the current ratings could be lower for applications with light loads, provided the ss capacitor is sized appropriately to limit inductor currents at start-up. diode selection schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the lt3579. choose a schottky with low parasitic capacitance to reduce reverse current spikes through the power switch of the lt3579. the diodes inc. mbrm360 is a very good choice with a 60v reverse voltage rating and an average forward current of 3a. output capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small packages. x5r or x7r type are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. a 22f to 47f output capacitor is suficient for most applications, but systems with low output currents may need only 4.7f to 22f. always use a capacitor with a suficient voltage rating. many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. tantalum polymer or os-con capacitors can be used, but it is likely that these capacitors will occupy more board area than a ceramic, and will have higher esr with greater output ripple. input capacitor selection ceramic capacitors make a good choice for the input decoupling capacitor, c vin , which should be placed as close as possible to the v in pin of the lt3579. this ensures that the voltage seen at the v in pin of the lt3579 remains a nearly lat dc voltage. a 1f to 4.7f input capacitor is suficient for most applications. a ceramic bypass capacitor, c pwr , should also be placed as close as possible to the input of the inductor. this ensures that the inductor ripple current is supplied from the bypass capacitor and provides a nearly lat dc voltage to the input of the voltage converter. a 4.7f to 10f input power capacitor is suficient for most applications. downloaded from: http:///
lt3579/lt3579-1 28 35791fa for more information www.linear.com/lt3579 appendix table 6 shows a list of several ceramic capacitor man- ufacturers. consult the manufacturers for detailed infor- mation on their entire selection of ceramic parts. table 6. ceramic capacitor manufacturers tdk www.tdk.com murata www.murata.com taiyo yuden www.t-yuden.com pmos selection an external pmos, controlled by the lt3579s gate pin, can be used to facilitate input or output disconnect. the gate pin turns on the pmos gradually during start-up (see soft-start of external pmos in the operation sect ion), and turns the pmos off when the lt3579 is in shutdown or in fault. the use of the external pmos, controlled by the gate pin, is particularly beneicial when dealing with unintended output shorts in a boost regulator. in a conventional boost regulator, the inductor, schottky diode, and power switches are susceptible to damage in the event of an output short to ground. using an external pmos in the boost regulators power path (path from v in to v out ) controlled by the gate pin, will serve to disconnect the input from the output when the output has a short to ground, thereby helping save the ic, and the other components in the power path from damage. the pmos chosen must be capable of handling the maximum input or output current depending on whether the pmos is used at the input (see figure 12) or the output (see figure 13). ensure that the pmos is biased with enough source to gate voltage (v sg ) to enhance the device into the triode mode of operation. the higher the v sg voltage that biases the pmos, the lower the r dson of the pmos, thereby lowering power dissipation in the device during normal operation, as well as improving the eficiency of the application in which the pmos is used. the following equations show the relationship between r gate (see block diagram) and the desired v sg that the pmos is biased with: v sg = v s r gate r gate + 2k ? if v gate < 2v 933a ? r gate if v gate > 2v ?? ? ? ? when using a pmos, it is advisable to conigure the speciic application for undervoltage lockout (see the operations section). the goal is to have v in get to a certain minimum voltage where the pmos has suficient headroom to attain a high enough v sg , which prevents it from entering the saturation mode of operation during start-up.figure 6 shows the pmos connected in series with the output to act as an output disconnect during a fault condition. the schottky diode from the v in pin to the gate pin is optional and helps turn off the pmos quicker in the event of hard shorts. the resistor from v in to the shdn pin sets a uvlo of 4v for this application. connecting the pmos in series with the output offers certain advantages over connecting it in series with the input: ? since the load current is always less than the input current for a boost converter, the current rating of the pmos goes down when connected in series with the output as opposed to the input. ? a pmos in series with the output can be biased with a higher overdrive voltage than a pmos used in series with the input, since v out > v in . this higher overdrive results in a lower r dson for the pmos, thereby improving the eficiency of the regulator. in contrast, an input connected pmos works as a simple hot-plug controller (covered in more detail in the hot-plug section). the input connected pmos also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the lt3579 with other compatible ics (see figure 12). downloaded from: http:///
lt3579/lt3579-1 29 35791fa for more information www.linear.com/lt3579 appendix table 7 shows a list of several discrete pmos manufa- cturers. consult the manufacturers for detailed information on their entire selection of pmos devices. table 7. discrete pmos manufacturers vishay www.vishay.com fairchild semiconductor www.fairchildsemi.com central semiconductor www.centralsemi.com compensation ? adjustment to compensate the feedback loop of the lt3579, a series resistor-capacitor network in parallel with an optional single capacitor must be connected from the v c pin to gnd. for most applications, choose a series capacitor in the range of 1nf to 10nf with 2.2nf being a good starting value. the optional parallel capacitor should range in value from 22pf to 180pf with 47pf being a good starting value. the compensation resistor, r c , is usually in the range of 5k to 50k. a good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor r c . with the series and parallel capacitors at 2.2nf and 47pf respectively, adjust the potentiometer while observing the transient response and the optimum value for r c can be found. figures 17a to 17c illustrate this process for the circuit of figure 20 with a load current stepped between 0.7a and 1.5a. figure 17a shows the transient response with r c equal to 1k. the phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. in figure 17b, the value of r c is increased to 3.5k, which results in a more damped response. figure 17c shows the results when r c is increased further to 8k. the transient response is nicely damped and the compensation procedure is complete. compensation ? theory like all other current mode switching regulators, the lt3579 needs to be compensated for stable and eficient operation. two feedback loops are used in the lt3579: a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. figure 17a. transient response shows excessive ringing figure 17b. transient response is better figure 17c. transient response is well damped 100s/div v out 500mv/div ac coupled i l 2a/div i load 1a/div 35791 f17a r c = 1k 100s/div v out 500mv/div ac coupled i l 2a/div i load 1a/div 35791 f17b r c = 3.5k 100s/div v out 500mv/div ac coupled i l 2a/div i load 1a/div 35791 f17c r c = 8k downloaded from: http:///
lt3579/lt3579-1 30 35791fa for more information www.linear.com/lt3579 as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 18 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by a combination of the equivalent transconductance ampliier g mp and the current controlled current source (which converts i vin to v in v out i vin ). g mp acts as a current source where the peak input current, i vin , is proportional to the v c voltage. appendix 1.215v reference i vin ? v in v out ? i vin v out c out c pl r esr r l r o r c c c c f r1 fb r2r2 C + C + 35791 f18 g mp g ma c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductor amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out /i loadmax r o : output resistance of gma r1, r2; feedback resistor divider network r esr : output capacitor esr : converter efficiency (~90% at higher currents) figure 18. boost converter equivalent model note that the maximum output currents of g mp and g ma are inite. the output of the g mp stage is limited by the minimum switch current limit (see electrical speciications) and g ma is nominally limited to about 12a. from figure 18, the dc gain, poles and zeros can be calculated as follows: dc gain: a dc = g ma ? r o ? g mp ? ? v in v out ? r l 2 ? 0.5r 2 r 1 + 0.5r 2 output pole: p1 = 2 2 ? ? r l ? c out error amp pole: p2 = 1 2 ? ? r o + r c ( ) ? c c error amp zero: z1 = 1 2 ? ? r c ? c c esr zero: z2 = 1 2 ? ? r esr ? c out rhp zero: z3 = v in 2 ? r l 2 ? ? v out 2 ? l high frequency pole: p3 > f s 3 phase lead zero: z4 = 1 2 ? ? r 1 ? c pl phase lead pole: p4 = 1 2 ? ? r 1 ? 0.5r 2 r 1 + 0.5r 2 ? c pl error amp filter pole: p5 = 1 2 ? ? r c ? r o r c + r o c f , c f < c c 10 downloaded from: http:///
lt3579/lt3579-1 31 35791fa for more information www.linear.com/lt3579 appendix the current mode zero (z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. using the circuit in figure 20 as an example, table 8 shows the parameters used to generate the bode plot shown in figure 19. table 8. bode plot parameters parameter value units comment r l 7 application specific c out 30 f application specific r esr 2 m application specific r0 305 k not adjustable c c 2200 pf adjustable c f 47 pf optional/adjustable c pl 0 pf optional/adjustable r c 8 k adjustable r1 130 k adjustable r2 14.6 k not adjustable v out 12 v application specific v in 5 v application specific g ma 250 mho not adjustable g mp 28 mho not adjustable l 2.2 h application specific f osc 1.0 mhz adjustable from figure 19, the phase is C134 when the gain reaches 0db giving a phase margin of 46. the crossover frequency is 8khz, which is more than three times lower than the frequency of the rhp zero z3 to achieve adequate phase margin. figure 19. bode plot for example boost converter figure 20. 5v to 12v boost converter frequency (hz) 10 C20 gain (db) phase (deg) 60 80 100 120 4020 0 140 C360 C315 C180 C135 C90 C45 C225C270 0 100 10k 100k 1m 35791 f19 1k phase gain 46 at 8khz v out 12v1.7a c out 10f 3 l1 2.2h d1 v in 5v v in sw1 sw2 35791 f20 lt3579 86.6k 8k 130k 100k shdn fault fb gate clkout vc sync gnd ss rt 2.2nf 0.1f 47pf c in 22f downloaded from: http:///
lt3579/lt3579-1 32 35791fa for more information www.linear.com/lt3579 typical application ef?ciency and power loss 1mhz, 5v to 12v boost converter can survive output shorts output short transient response with 0.7a to 1.5a to 0.7a output load step load current (a) 0 20 efficiency (%) 80 9070 60 50 40 30 100 0 power loss (w) 2.4 2.82 1.6 1.2 0.8 0.4 3.2 0.25 1 1.25 1.5 1.75 2 0.5 35791 ta03 0.75 10s/div v out 10v/div clkout 2v/div i l 2a/div fault 5v/div 35791 ta05 100s/div v out 500mv/div ac coupled i l 2a/div i load 1a/div 35791 ta06 v in 5v l1 2.2h d1 c out1 10f c in 22f v out 12v1.7a c out 10f c in : 22f, 16v, x7r, 1210 c out1 , c out : 10f, 25v, x7r, 1210 d1: vishay ssb43l d2: central semi cmdsh-3tr l1: wrth we-pd 744771002 m1: siliconix si7123dn 100k 35791 ta03a 130k 6.3k 8k 2.2nf 0.1f 47pf 86.6k 200k v in m1 d2 sw1 sw2 v in fb clkout v c ss gnd gate fault sync rt shdn lt3579 downloaded from: http:///
lt3579/lt3579-1 33 35791fa for more information www.linear.com/lt3579 typical application l 2 3.3h 0.22f l1 3.3h d3 d2 d4 v out 3.3v1.8a (v bat = 3v) 3.1a (v bat = 9v) 3.4a (v bat 12v) v bat 3v to 33v (operating) 6v to 16v (start-up) 35791 ta07a 24.9k 8.25k 10k 174k 100k 200k 10k ? ? c out 47f 6 c vin 10f c110nf d115v m1 c pwr 4.7f 2 c2 4.7f c1: 10nf, 16v, x7r, 0603 c vin : 10f, 16v, x7r, 1206 c pwr , c2: 4.7f, 50v, x7r, 1210 c out : 47f, 6.3v, x7r, 1210 d1: central semi cmhz5245b-ltz d2: vishay ss5p6 d3: central semi cmmsh2-40 d4: central semi cmmsh2-40 l1, l2: wrth we-dd 744870003 m1: 2n7002 q1: mmbt3904 4.7nf 100pf v in sw1 sw2 lt3579 shdn fault clkout gate fb vc sync gnd ss rt q1 4.7nf 500khz sepic converter generates 3.3v from a 3v to 33v input load current (a) 0 10 efficiency (%) power loss (w) 50 60 70 8040 30 20 90 0 2 2.5 3 3.51.5 1 0.5 4 1.5 2 2.5 3 3.5 4 0.5 1 35791 ta08a v bat = 12v v bat = 3v ef?ciency and power loss 50ms/div v out 2v/div v bat 10v/div i l1 + i l2 1a/div 35791 ta08b transient response with 9v to 33v to 9v v b at glitch (r load = 1.5) downloaded from: http:///
lt3579/lt3579-1 34 35791fa for more information www.linear.com/lt3579 typical application v out C12v 1.2a c out 10f 2 l1 3.3h l2 3.3h c1 4.7f d1 v in 5v v in sw1 sw2 35791 ta14 lt3579 71.5k 20k 143k 100k fault shdn fb gate clkout vc sync gnd ss rt 1nf 0.22f 27pf c in 22f c in : 22f, 16v, x7r, 1210 c1: 4.7f, 25v, x7r, 1206 c out : 10f, 25v, x7r, 1210 d1: diodes inc b230al1, l2: cooper bussmann drq125-3r3-r load current (a) 0 20 efficiency (%) power loss (w) 60 70 80 9050 40 30 100 0 1.6 2 2.4 2.81.2 0.8 0.4 3.2 0.5 0.75 1 1.25 0.25 35791 ta15 1.2mhz, 5v to -12v inverting converter ef?ciency and power loss transient response with 0.5a to 1a to 0.5a output load step 100s/div v out 500mv/div ac coupled i l1 + i l2 1a/div i load 1a/div 35791 ta16 downloaded from: http:///
lt3579/lt3579-1 35 35791fa for more information www.linear.com/lt3579 v in 9v to 16v v out2 100v 330ma* v out1 67v 500ma* l1 10h c4 2.2f 2 c32.2f 2 c52.2f 2 c62.2f 2 c22.2f 3 c12.2f 3 c in : 10f, 25v, x7r, 1210 c1-c6: 2.2f, 50v, x7r, 1210 d1-d6: diodes inc sbr2a40p1 d7: central semi cmdsh-3tr d8: central semi cmdz5237b-ltz d9: diodes inc mbrm360 l1: wrth we-pd 7447710 m1: siliconix si7461dp m1** 100k c in 10f sw1 sw2 v in fb clkout v c ss gnd gate fault sync rt shdn lt3579 35791 ta17 383k 6.5k** 34k 470pf 2.2f 27pf 86.6k 536k v in d2 d8**8.2v d3 d5 d4 d6 d1 d9** *max total output power 22w (v in = 9v) 27w (v in = 12v) 33w (v in = 16v) **optional for output short circuit protection d7** typical application vfd (vacuum fluorescent display) power supply switches at 1mhz ef?ciency and power loss (v in = 12v) cycle-to-cycle total output power (w) 0 65 efficiency (%) power loss (w) 80 8575 70 90 0 3 42 1 5 5 20 25 30 10 35791 ta18 15 1s/div v out1 2v/div ac coupled sw1 20v/div v out2 2v/div ac coupled i l 1a/div 35791 ta19 danger high voltage! operation by high voltage trained personnel only downloaded from: http:///
lt3579/lt3579-1 36 35791fa for more information www.linear.com/lt3579 typical application 1mhz, 5v to 12v converter v in 5v c in 10f l1 4.7h c2 4.7f c1 4.7f c in : 10f, 16v, x7r, 1206 c1, c2: 4.7f, 25v, x7r, 1206 c out1 , c out2 : 10f, 25v, x7r, 1210 d1-d5: diodes inc sbr2a40p1 l1: vishay ihlp-2525cz-01-4r7 r1: 1.2k, 2w **if driving asymmetrical loads, place a 1.2k, 2w resistor from the +12v output to the C12v output for improved load regulation of the C12v output. 100k 35791 ta20 34k 86.6k 1nf 27pf d2 130k d5 r1**1.2k d3 d4 d1 c out 2 10f 2 v out 2 C12v0.8a* c out1 10f 2 v out1 12v0.8a* sw1 sw2 v in fb clkout v c ss gnd gate shdnsync rt fault lt3579 0.1f *max total output power = 9.6w ef?ciency and power loss load current (ma) 0 40 45 55 65 75 85 efficiency (%) power loss (w) 70 8060 50 90 0 0.9 1.2 1.5 1.8 2.1 2.4 2.70.6 0.3 3 100 400 500 200 35791 ta21 300 100s/div v out1 500mv/div ac coupled i l 1a/div v out2 500mv/div ac coupled 35791 ta22 transient response with 0.15a to 0.35a to 0.15a symmetrical output load step downloaded from: http:///
lt3579/lt3579-1 37 35791fa for more information www.linear.com/lt3579 typical application l2 4.7h l1 4.7h d2 d1 d3** m1** c pwr2 10f c vin2 4.7f c out1s 4.7f 2 c out1m 4.7f 2 v pwr 8v to 16v v in 3.3v to v pwr v out 24v5.1a* v out1 v out1 v pwr 0.22f c out 4.7f 2 c vin1 4.7f c pwr1, c pwr2 : 10f, 25v, x7r, 1210 c vin1, c vin2 : 4.7f, 25v, x7r, 1206 c out1m, c out1s, c out : 4.7f, 50v, x5r, 1210 d1, d2: central semi ctlsh5-40m833 d3: central semi ctlsh1-40m563 l1, l2: vishay ihlp-2525cz-01-4r7 m1: siliconix si7461dp c pwr1 10f 137k 35791 ta23 sw1 sw2 v in clkout gate v c ss gnd fb fault sync shdnrt lt3579-1 master sw1 sw2 v in clkout gate v c ss gnd fb fault sync shdnrt lt3579-1 slave 86.6k 6.4k** 7k 2.2nf 47pf 0.22f 5k 86.6k 21.5k 500k 100k 1mhz, 2-phase converter generates a 24v output from a 8v to 16v input and uses small components load current (a) 0 20 30 50 90 efficiency (%) power loss (w) 70 8060 40 100 0 3 4 5 6 72 1 8 1 0.5 3.5 4 4.5 2 1.5 35791 ta24 2.5 3 v in = 12v v in = 3.3v ef?ciency and power loss (v pwr = 12v) 100s/div v out 1v/div ac coupled i load 1a/div i l1 + i l2 5a/div 35791 ta25 transient response with 1.5a to 3.25a to 1.5a output load step (v pwr = 12v and v in = 3.3v) *max output current v pwr = 8v v pwr = 12v v pwr = 16v v in = 3.3v to 5v 2.4a 3.7a 5.1a v in = v pwr 2.2a 3.1a 3.9a **optional for output short circuit protection downloaded from: http:///
lt3579/lt3579-1 38 35791fa for more information www.linear.com/lt3579 typical application v in 2.8v to 4.2v l1 0.47h d1 c out1 22f c in 10f v out 5v2a c out 22f c in : 10f, 16v, x7r, 1206 c out1 , c out : 22f, 16v, x7r, 1210 d1: central semi ctlsh3-30m833 l1: vishay ihlp-2020bz-01-r47 m1: siliconix si7123dn 100k 35791 ta26 43.5k 10k 6.34k 2.2nf 22nf 47pf 43.2k m1 sw1 sw2 v in fb clkout v c ss gnd gate shdnsync rt fault lt3579 2mhz, boost converter with output disconnect generates a 5v output from 2.8v to 4.2v input ef?ciency and power loss load current (a) 0 20 30 50 90 efficiency (%) power loss (w) 70 8060 40 100 0 0.9 1.2 1.5 1.8 2.10.6 0.3 2.4 1 0.5 2.5 2 1.5 35791 ta27 v in = 3.3v 100s/div v out 200mv/div ac coupled i load 1a/div i l 1a/div 35791 ta28 transient response with 0.8a to 1.8a to 0.8a output load step (v in = 3.3v) downloaded from: http:///
lt3579/lt3579-1 39 35791fa for more information www.linear.com/lt3579 package description fe20 (cb) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 detail a detail a is the part of the lead frame feature for reference only no measurement purpose 11 12 14 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation cb detail a 0.60 (.024) ref 0.28 (.011) ref downloaded from: http:///
lt3579/lt3579-1 40 35791fa for more information www.linear.com/lt3579 package description 4.00 0.10 (2 sides) 1.50 ref 5.00 0.10 (2 sides) note:1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 19 20 12 bottom viewexposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notchr = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd20) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.65 0.05 2.50 ref 4.10 0.055.50 0.05 1.50 ref 3.10 0.05 4.50 0.05 package outline r = 0.05 typ 2.65 0.10 3.65 0.10 3.65 0.05 0.50 bsc ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) downloaded from: http:///
lt3579/lt3579-1 41 35791fa for more information www.linear.com/lt3579 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 05/14 clariied electrical speciications clariied table 1 clariied table 2 clariied table 3 clariied table 8 4 1314 15 30 downloaded from: http:///
lt3579/lt3579-1 42 35791fa for more information www.linear.com/lt3579 ? linear technology corporation 2010 lt 0514 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3579 related parts part number description comments lt3581 3.3a (i sw ), 42v, 2.5mhz, high eficiency step-up dc/dc converter v in : 2.5v to 22v, v out(max) = 42v, i q = 1.9ma, i sd = < 1a, 4mm 3mm dfn-14, msop-16e lt3580 2a (i sw ), 42v, 2.5mhz, high eficiency step-up dc/dc converter v in : 2.5v to 32v, v out(max) = 42v, i q = 1ma, i sd = < 1a, 3mm 3mm dfn-8, msop-8e lt3479 3a (i sw ), 40v, 3.5mhz, high eficiency step-up dc/dc converter v in : 2.5v to 24v, v out(max) = 40v, i q = 5ma, i sd = < 1a, 4mm 3mm dfn-14, tssop-16e typical application 1mhz sepic converter generates a 12v output from a 9v to 16v input d1 l 2 6.8h 0.22f 47pf l1 6.8h v out 12v 1.9a* c vin 4.7f v in 3.3v to v pwr v pwr 9v to 16v v in sw1 sw2 35791 ta29 lt3579 86.6k 9.53k 130k c1 4.7f shdn fault clkout gate fb vc sync gnd ss rt 2.2nf ? ? c out 10f 3 100k c pwr 4.7f c pwr : 4.7f, 25v, x7r, 1206 c vin : 4.7f, 25v, x7r, 1206 c1: 4.7f, 25v, x7r, 1206 c out : 10f, 25v, x7r, 1210 d1: diodes inc mbrm360l1, l2: cooper bussmann drq125-6r8-r line regulation (v in = 5v, i out = 1a) = 0.017%/v load regulation (v pwr = 12v, v in = 5v) = C0.23%/a *max output current v pwr = 9v v pwr = 12v v in = 3.3v to 5v 1.6a 1.9a v in = v pwr 1.4a 1.4a load current (a) 0 20 efficiency (%) power loss (w) 60 70 80 9050 40 30 100 0 1.6 2 2.4 2.81.2 0.8 0.4 3.2 0.75 1 1.25 1.5 1.75 2 0.25 0.5 35791 ta30 v pwr = 12v v in = 5v ef?ciency and power loss downloaded from: http:///

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